Boston Area Architecture Workshop (BARC-2005)

Brown University
Andrew's Dining Hall

January 21, 2005

8:15am-9:00am: Continental Breakfast

9:00am: Introduction

9:15am-10:15am: Architecture Simulation and Multiprocessing (Session Chair: Martin Herbordt)
METERG: An Architectural Support to Provide Worst-case Performance Guarantee on Multiprocessor Platforms, J. W. Lee, K. Asanovic, MIT
Simulating a Chip Multiprocessor with a Symmetric Multiprocessor, K. Barr, C. Weaver, R. Matas-Navarro, T. Juan, J. Emer, MIT and Intel Massachusetts
UNUM: A General Microprocessor Framework Using Guarded Atomic Actions, N. Dave, M. Pellauer, Arvind, MIT

10:15-10:45am: Break

10:45am-12:05pm: Reliable Systems and Emerging Architectures (Session Chair: Eliot Moss)
Computing Architecture Vulnerability Factors for Address-Based Structures, A. Biswas, J. Emer, P. Racunas, S. Mukherjee, Intel Massachusetts
Dynamic Fault Prevention in Out-of-Order Processors, B. Gojman, R. I. Bahar, Brown University
Balancing Performance and Reliability in the Memory Hierarchy, G. Asadi, V. Sridharan, M. B. Tahoori, D. Kaeli, Northeastern University
Wire Streaming Processors on 2-D Nanowire Fabrics, T. Wang, M. Ben-Naser, Y. Guo, C. A. Moritz, UMass, Amherst

12:05pm-1:15pm: Buffet Lunch

1:15pm-1:45pm: Keynote (Session Chair: Joel Emer)
Performance, Energy and Reliability Tradeoffs in Deep Sub-micron CMOS, Wayne Burleson, University of Massachusetts, Amherst

1:45pm-2:45pm: Cache and Memory Design (Session Chair: Dan Leibholz)
Event-Trace Simulation Results of the DASAT Cache System for Wire-delay Dominated L0 Caching, M. Y. Maxwell, J. E. B. Moss, C. C. Weems, UMass, Amherst
A Step-by-Step Design and Analysis of Low Power Caches for Embedded Processors, M. Ben-Naser, C. A. Moritz, UMass, Amherst
BCachet: An Efficient Buffer Management Method for Cachet, B. Kim, Arvind, MIT

2:45pm-3:15pm: Break

3:15pm-4:25pm: Temperature, Power, and Performance (Session Chair: Krste Asanovic)
Temperature Aware Floorplanning, Y. Han, I. Koren, C. A. Moritz, UMass, Amherst
When is Criticality Critical?, V. Stojanovic, R. I. Bahar, R. Weiss, Brown University and Hampshire College
Adaptive Computing, Gus Uht, University of Rhode Island

4:25pm-5:25pm: Architectures and Algorithms (Session Chair: David Kaeli)
Making FPGAs a Cost-Effective Computing Architecture, T. VanCourt, Y. Gu, M. Herbordt, Boston University
Transaction Processing in the Fresh Breeze Multiprocessor, J. B. Dennis, MIT
A Quantitative Analysis of Stream Algorithms on RAW Fabrics, H. Hoffmann, A. Agarwal, MIT

5:25pm-5:30pm: Concluding Remarks