00001 // This is core/vil1/vil1_32bit.cxx 00002 #ifdef VCL_NEEDS_PRAGMA_INTERFACE 00003 #pragma implementation 00004 #endif 00005 //: 00006 // \file 00007 // \author fsm 00008 00009 00010 #include "vil1_32bit.h" 00011 #include <vil1/vil1_stream.h> 00012 #include <vxl_config.h> 00013 00014 typedef vxl_uint_8 word8; 00015 typedef vxl_uint_32 word32; 00016 00017 unsigned vil1_32bit_read_big_endian(vil1_stream *s) 00018 { 00019 word8 bytes[4]; 00020 s->read(bytes, sizeof bytes); 00021 return (word32(bytes[0])<<24) + (word32(bytes[1])<<16) + (word32(bytes[2])<<8) + (word32(bytes[3])); 00022 } 00023 00024 unsigned vil1_32bit_read_little_endian(vil1_stream *s) 00025 { 00026 word8 bytes[4]; 00027 s->read(bytes, sizeof bytes); 00028 return (word32(bytes[3])<<24) + (word32(bytes[2])<<16) + (word32(bytes[1])<<8) + (word32(bytes[0])); 00029 } 00030 00031 void vil1_32bit_write_big_endian(vil1_stream *s, unsigned w) 00032 { 00033 word8 bytes[4]; 00034 bytes[0] = w >> 24; 00035 bytes[1] = w >> 16; 00036 bytes[2] = w >> 8; 00037 bytes[3] = w >> 0; 00038 s->write(bytes, sizeof bytes); 00039 } 00040 00041 void vil1_32bit_write_little_endian(vil1_stream *s, unsigned w) 00042 { 00043 word8 bytes[4]; 00044 bytes[0] = w >> 0; 00045 bytes[1] = w >> 8; 00046 bytes[2] = w >> 16; 00047 bytes[3] = w >> 24; 00048 s->write(bytes, sizeof bytes); 00049 }
1.5.1