R. Iris Bahar

email: Iris_Bahar@Brown.EDU
office: Barus and Holley 322
phone: (401) 863-1430
fax: (401) 863-1157
mailing address:
Box D, Engineering
Brown University
Providence, RI 02912

Principal Investigations: Computer Architecture, Low-Power Design, and Computer Aided Design, Nanosystem Design

Here is a brief overview of our group

Go to the BARC2005 Webpage for more information on the Boston Area Computer Architecture Workshop that took place in Providence, RI on January 21, 2005.

Courses Taught:

EN0164: Design of Computing Systems

EN0291-S08: Synthesis of VLSI Systems

EN0292-S10: Advanced Computer Architecture

EN0291-S010: Nanosystem Design

EN160: Design and Implementation of VLSI Systems

Academic History

Ph.D in Electrical Engineering

University of Colorado, Boulder
Dissertation: Methods for Timing Analysis and Logic Synthesis to Decrease Power Dissipation
Advisor: Fabio Somenzi

M.S. in Electrical Engineering

University of Illinois, Urbana
Thesis: Speeding Up Logic Level Fault Simulation Using Efficient Module Representations

B.S. in Computer Engineering

University of Illinois, Urbana

Graduate Students:

Yu Bai (Graduated Aug. 2004, now working for Intel)
Hui-Yuan Song (Graduated Sept. 2005, now working for Magma-DA)
Vladimir Stojanovic (Graduated May 2006)

Tali Moreshet
Kundan Nepal
Desta (Mickey) Tadesse
Nuno Alves

Selected Publications:

D. Tadesse, D. Sheffield, E. Leng, R. I. Bahar, and J. Grodstein, " Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models," Design Automation and Test in Europe, April 2007.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, A. Zaslavsky, " Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits," Design Automation and Test in Europe, April 2007.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, A. Zaslavsky, " MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits," IEEE Micro, Vol. 26, No. 5, September/October 2006, pp. 19-27. (preprint version).

Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss, "A Cost-Effective Implementation of an ECC-protected Instruction Queue for Out-of-Order Microprocessors," Design Automation Conferenced, July 2006.

K. Nepal, R. I. Bahar, J. Mundy, W. Patterson, A. Zaslavsky, "Optimizing Noise-Immune Nanoscale Circuits using Principles of Markov Random Fields," Great Lakes Symposium on VLSI, April 2006.

H. Y. Song, K. Nepal, R. I. Bahar, J. Grodstein, " Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations," IEEE Transactions on CAD, Vol. 25, No. 9, September 2006, pp. 1815-1830 (preprint version).

K. Nepal, R. I. Bahar, J. Mundy, W. Patterson, A. Zaslavsky, "Designing MRF based Error Correcting Circuits for Memory Elements,", Design, Automation and Test in Europe (DATE), March 2006.

D. Tadesse, M. Black, D. Sheffield, R. I. Bahar, J. Grodstein, "Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), February 2006.

T. Moreshet, R. I. Bahar, M. Herlihy, "Energy Reduction in Multiprocessor Systems using Transactional Memory,"International Symposium on Low Power Electronics and Design (ISLPED), August 2005.

K. Nepal, R. I. Bahar, J. Mundy, W. Patterson, A. Zaslavsky, "Designing logic circuits for probabilistic computation in the presence of noise", Design Automation Conference, June 2005.

R. I. Bahar, H. Y. Song, K. Nepal, J. Grodstein, "Symbolic Failure Analysis of Complex CMOS Circuits due to Excessive Leakage Current and Charge Sharing," IEEE Transactions on CAD, Vol. 24, No. 4, April 2005, pp. 502-515. (preprint version).

N. Mehta, B. Singer, R. I. Bahar, M. Leuchtenburg, and R. Weiss, "Fetch Halting on Critical Load Misses," International Conference on Computer Design, San Jose, CA, October 2004.

Y. Bai and R. I. Bahar, "Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm," International Conference on Computer Design, San Jose, CA, October 2004.

R. I. Bahar, J. Chen, and J. Mundy, "A Probabilistic-Based Design for Nanoscale Computation," Chapter 5 in, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, Edited by S. Shukla and R.I. Bahar, Kluwer Academic Publishers, 2004 (preprint)

T. Moreshet and R. I. Bahar, "Effects of Speculation on Performance and Issue Queue Design," IEEE Transaction on VLSI, Vol. 12, No. 10, October 2004, pp. 1123-1125 (preprint version)

Y. Bai and R. I. Bahar, "A Low Power In-Order/Out-of-Order issue Queue," ACM Transactions on Architecture and Code Optimization, Vol. 1, No. 2, June 2004

K. Nepal, H. Y. Song, R. I. Bahar, and J. Grodstein, "RESTA: A Robust and Extendable Symbolic Timing Analysis Tool," Great Lakes Symposium on VLSI, Boston, MA, April 2004

R. I. Bahar, J. Mundy, and J. Chen, "A Probabilistic-Based Design Methodology for Nanoscale Computation," International Conference on Computer-Aided Design, San Jose, CA, November 2003

H.Y. Song, S. Bohidar, R. I. Bahar, and J. Grodstein, "Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current," International Conference on Computer Design, San Jose, CA, October 2003

Tali Moreshet and R. Iris Bahar, "Power-Aware Issue Queue Design for Speculative Instructions," Design Automation Conference, Anaheim, CA, June 2003.

Yu Bai and R. Iris Bahar, "A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors," International Symposium on VLSI, Tampa, FL, February 2003.

Eric Chi, A. Michael Salem, R. Iris Bahar, and Richard Weiss, "Combining Software and Hardware Monitoring for Improved Power and Performance Tuning," Workshop on Interaction Between Compilers and Computer Architecture (INTERACT), held in conjunction with HPCA, Anaheim, CA, February 2003.

Hui-Yuan Song, R. Iris Bahar, and Joel Grodstein, "Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations," International Workshop on Logic and Synthesis, New Orleans, LA, June 2002.

Tali Moreshet and R. Iris Bahar, "Complexity-Effective Issue Queue Design Under Load-Hit Speculation," Workshop on Complexity-Effective Design, held in conjunction with the International Symposium on Computer Architecture, Anchorage, AK, May 2002.

R. Iris Bahar and Srilatha Manne, "Power and Energy Reduction Via Pipeline Balancing," International Symposium on Computer Architecture, Goteborg, Sweden, July 2001.

Hui-Yuan Song, R. Iris Bahar and Joel Grodstein, "An ADD-Based Symbolic Analysis of Leakage Current in CMOS Circuits," International Workshop on Logic and Synthesis, Granlibakken, CA, June 2001.

Roberto Maro, Yu Bai, and R. I. Bahar, "Dynamically Reconfiguring Processor Resources \\ to Reduce Power Consumption in High-Performance Processors," Workshop on Power-Aware Computer Systems, Cambridge, MA, November 2000.

B. R. Fisk and R. I. Bahar, "The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency," IEEE International Conference on Computer Design, Austin, TX, October 1999.

R. I. Bahar, E. T. Lampe, E. Macii, "Power Optimization of Technology-Dependent Circuits Based on Symbolic Computation of Logic Implications," to appear in ACM Transactions on Design Automation of Electronic Systems.

G. Albera, R. I. Bahar, "Power/Performance Advantages of a Victim Buffer in High-Performance Processors," IEEE Volta International Workshop on Low Power Design, Como, Italy, March 1999.

R. I. Bahar, D. Grunwald, B. Calder, "A Comparison of Software Code Reordering and Victim Buffers," ACM SIGARCH Computer Architecture News, March 1999.

R.Iris Bahar, Gianluca Albera, Srilatha Manne, "Power and Performance Tradeoffs using Various Caching Strategies," International Symposium on Low Power Electronics and Design, Monterey, CA, August 1998.

R. I. Bahar, G. Albera, "Performance Analysis of Wrong-Path Data Cache Accesses," Workshop on Performance Analysis and its Impact on Design, held in conjunction with the International Symposium on Computer Architecture, Barcelona, Spain, June 1998.

R.I. Bahar, M. Burns, G.D. Hachtel, E. Macii, H. Shin, F. Somenzi, "Symbolic Computation of Logic Implications for Technology-Dependent Low-Power Synthesis," International Symposium on Low Power Electronics and Design, Monterey, CA, August 1996.

R.I. Bahar, F. Somenzi, "Boolean Techniques for Low Power Driven Re-synthesis," ICCAD-95: ACM/IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1995.

R.I. R.I. Bahar, G.D. Hachtel, E. Macii, F. Somenzi, "A Symbolic Method to Reduce Power Consumption of Circuits Containing False Paths," ICCAD-94: ACM/IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1994.

R.I. Bahar, H. Cho, G. D. Hachtel, E. Macii, F. Somenzi, "An Application of ADD-Based Timing Analysis to Combinational Low Power Re-Synthesis" IWLP-94: ACM/IEEE International Workshop on Low Power Design, Napa, CA, April 1994., pp. 39-44

R.I. Bahar, H. Cho, G. D. Hachtel, E. Macii, F. Somenzi, "Timing Analysis of Combinational Circuits Using ADD's," EDAC-94: IEEE European Conference on Design Automation, Paris, France, February 1994., pp. 625-629

R.I. Bahar, E.A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, F. Somenzi, "Algebraic Decision Diagrams and their Applications," ICCAD-93: ACM/IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1993.

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Last modified: Thu Aug 8 15:11:34 EDT 1996