Publications

2008

K. Nepal, R. I. Bahar, J. Mundy, W. Patterson, A. Zaslavsky, “Designing Nanoscale Logic Circuits Based on Principles of Markov Random Fields,” Chapter 12 in Emerging Nanotechnologies: Test, Defect Tolerance and Reliability, M. Tehranipoor, editor, Springer Publishers, 2008, ISBN: 978-0-387-74746-0.

M. B. Tahoori, N. K. Jha, R. I. Bahar, “Testing Aspects of Nanotechnology Trends,” Chapter 17 in Systems on Chip Test Architectures:  Nanometer Design for Testability, L. T. Wang, C. Stroud, and N. Touba, editors, Elsevier Publishers (Morgan Kaufmann), 2008, ISBN:  978-0-12-373973-5.

D. Tadesse, J. Grodstein, R. I. Bahar, “Fast Measurement of the `Non-deterministic Zone’ in Microprocessor Debug using Maximum Likelihood Estimation,” IEEE VLSI Test Symposium, April 2008. 

R. I. Bahar and K. Chakrabarty, “Guest Editorial,” ACM Journal of Emerging Technologies in Computing (JETC), Vol. 25, No. 5, April 2008.

C. Ferri, A. Viescas, T. Moreshet, R.I. Bahar and M. Herlihy, “Energy Efficient Synchronization Techniques for Embedded Architectures,” ACM/IEEE Great Lakes Symposium on VLSI, May 2008. 

N. Alves, K. Nepal, R. Iris Bahar, J. Dworak, “Using Implications for Online Error Detection,” IEEE North Atlantic Test Workshop, May 2008.

A. Calimera, R. I. Bahar, E. Macii, M. Poncino, “Temperature-Insensitive Synthesis using Multi-Vt Libraries,” ACM/IEEE Great Lakes Symposium on VLSI, May 2008.

N. Alves, K. Nepal, J. Dworak, R. I. Bahar, “Detecting Multi-cycle Errors using Invariance Information,”  IEEE European Test Symposium, May 2008.

C. Ferri, A. Viescas, T. Moreshet, R.I. Bahar and M. Herlihy, “Energy Implications of Transactional Memory for Embedded Architectures,” Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM)., April 2008.

2007

R. I. Bahar, J. Harlow, D. Hammerstrom, W. H. Joyner Jr., C. Lau, D. Marculescu, A. Orailoglu, M. Pedram, “Architectures for Silicon Nanotechnology and Beyond,” IEEE Computer, Vol. 40, No. 1, January 2007, pp. 25-33.

C. Ferri, T. Moreshet, R. I. Bahar, L. Benini, and M. Herlihy, “A Framework for Supporting Transactional Memory in a MPSoC Environment,” Boston Area Architecture Workshop (BARC), January 2007.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, “Designing Nanoscale Logic Circuits based on Markov Random Fields,” Journal of Electronic Testing: Theory and Applications, Vol. 23, No. 2, March 22, 2007, pp. 255-266.

K. Nepal, R. I. Bahar,  J. Mundy, W. R. Patterson, and A. Zaslavsky, “Techniques for Designing Noise-Tolerant Multi-level Combinational Circuits,” IEEE/ACM Design Automation and Test in Europe Conference, April 2007, pp. 576-581.

D. Tadesse, D. Sheffield , E. Lenge, R. I. Bahar, and J. Grodstein, “Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models,” IEEE/ACM Design Automation and Test in Europe Conference, April 2007, pp. 1018-1023.

H. Li, J. Mundy, W. R. Patterson, D. Kazazis, A. Zaslavsky, R. I. Bahar, “Prediction of soft errors in nanoscale CMOS circuits,” Nanoelectronic Devices for Defense & Security(NANO-DDS) Conference, June 2007.

H. Li, J. Mundy, W. R. Patterson, D. Kazazis, A. Zaslavsky, R. I. Bahar, “Thermally-induced soft errors in nanoscale CMOS circuits,” IEEE/ACM Symposium on Nanoscale Architectures(NANOARCH), October 2007, pp. 62-69.

C. Ferri, S. Reda, and R. I. Bahar, “Strategies for Improving the Parametric Yield and Profits of 3D ICs,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2007, pp. 220-226.

2006

T. Moreshet, R. I. Bahar, and M. Herlihy, “Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks,” Boston Area Architecture Workshop (BARC), North Kingston, RI, January 2006.

T. Moreshet, R. I. Bahar, and M. Herlihy, “Energy-Aware Microprocessor Synchronization: Transactional Memory vs. Locks,” Workshop on Memory Performance Issues, February 2006.

V. Stojanovic, R. I. Bahar, J. Dworak, R. Weiss, “A Cost-Effective Implementation of an ECC-Protected Instruction Queue for Out-of-Order Microprocessors,” Workshop on High Performance Computing Reliability Issues, February 2006.

D. Tadesse, R. I. Bahar, and J. Grodstein, “Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models,” ACM/IEEE International Workshop on Timing Issues, February 2006.

K. Nepal, R. I. Bahar, J. Mundy,W. R. Patterson, and A. Zaslavsky, “Designing MRF based Error Correcting Circuits for Memory Elements,” IEEE/ACM Design Automation and Test in Europe Conference, March 2006, pp. 792-793.

H. Li, J. Mundy, W. Patterson, D. Kazazis, A. Zaslavsky and R. I. Bahar, “A Model for Soft Errors in the Subthreshold CMOS Inverter,” Workshop on SELSE 2, System Effects of Logic Soft Errors, April 2006.

R. I. Bahar, “Nanoscale Circuits and Architectures for Probabilistic Computation in the Presence of Noise,” Foundations of Nanoscience Conference (FNANO), Snowbird, UT, April 2006. Invited paper.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, “Optimizing Noise-Immune Logic Circuits using Principles of Markov Random Fields,” IEEE/ACM Great Lakes Symposium on VLSI, May 2006, pp. 149-152.

R. I. Bahar and Stephen Edwards, “Guest Editorial,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 25, No. 5, May 2006, pp. 741-742.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, “Techniques for MRF based implementation of multi-level combinational circuits,” IEEE Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH 2006), June 2006.

T. Moreshet, R. I. Bahar, and M. Herlihy, “Energy Implications of Multiprocessor Synchronization,” ACM SPAA’06: Symposium on Parallelism in Algorithms and Architectures, August 2006.

H.Y. Song, K. Nepal, R. I. Bahar, J. Grodstein, “Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 25, No. 9, September 2006, pp.1815–1830.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, “The MRF Reinforcer:  A Probabilistic Element for Space Redundancy in Nanoscale Circuits,” IEEE MICRO, Vol. 26, No. 5, September/October 2006, pp. 19–27.

R. I. Bahar, “Trends and Future Directions in Nano Structure Based Computing and Fabrication,” IEEE/ACM International Conference on Computer Design, San Jose, CA, October 2006, pp. 522-527. Invited paper.

C. Ferri, T. Moreshet, R. I. Bahar, L. Benini, and M. Herlihy, “A Hardware/Software Framework for Supporting Transactional Memory in a MPSoC Environment,” Workshop on Design, Architecture and Simulation of Chip Multi-Processors (dasCMP2006), December 2006. Also published in ACM SIGARCH Computer Architecture News, Vol. 35, No. 1, March 2007, pp. 47-54
 

2005

B. Gojman, R. I. Bahar, “Dynamic Fault Prevention in Out-of-Order Processors,” Boston Area Architecture Workshop (BARC), Providence, RI, January, 2005.

V. Stojanovic, R. I. Bahar, R. Weiss, “When is Criticality Critical?” Boston Area Architecture Workshop (BARC), Providence, RI, January, 2005.

R. I. Bahar, H. Y. Song, K. Nepal, J. Grodstein, “Symbolic Failure Analysis of Complex CMOS Circuits due to Excessive Leakage Current and Charge Sharing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits, Vol. 24, No. 5, April 2005, pp. 502-515.

B. Gojman, V. Stojanovic , R. I. Bahar, R. Weiss, “Techniques for Fault Reduction in Out-of-Order Microprocessors,” International Workshop on Logic and Synthesis (IWLS), Lake Arrowhead, CA, June 2005.

K. Nepal, R. I. Bahar, J. Mundy, W. R. Patterson, and A. Zaslavsky, “Designing Logic Circuits for Probabilistic Computation in the Presence of Noise,” IEEE/ACM Design Automation Conference, June 2005, pp. 485-490.

R. I. Bahar, M. B. Tahoori, S. K. Shukla, and F. Lombardi, “Guest Editors’ Introduction” Challenges for Reliable Design at the Nanoscale,” IEEE Design and Test of Computers, Vol. 22, No. 4, July-August 2005, pp. 295-297.

2004

Y. Bai, and R. I. Bahar, “Reducing Power with a Dynamically Reconfigurable Issue Queue,” Boston Area Architecture Workshop (BARC-2004), Boston, MA, January, 2004.

T. Moreshet, M. Herlihy, R. Iris Bahar, and Richard Weiss. “Reducing Power with a Dynamically Reconfigurable Issue Queue,” Boston Area ArchitectureWorkshop (BARC-2004), Boston, MA, January, 2004.

K. Nepal, H. Y. Song, R. I. Bahar, and J. Grodstein, “RESTA: A Robust and Extendable Symbolic Timing Analysis Tool,” IEEE/ACM Great Lakes Symposium on VLSI, Boston, MA, April 2004, pp. 407-412.

R. I. Bahar, J. Chen, J. Mundy, “A Probabilistic-Based Design for Nanoscale Computation,” Chapter 5 in, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, Springer, 2004, ISBN: 978-1-4020-8067-8.

S. Shukla and R. I. Bahar, editors, Nano, Quantum and Molecular Computing: Implications to High Level Design and Validation, Springer, 2004, ISBN: 978-1-4020-8067-8.

Y. Bai and R. I. Bahar, “A Low Power In-Order/Out-of-Order Issue Queue,” ACM Transactions on Architecture and Code Optimization, Vol. 1, No. 2, June 2004, pp. 152-179.

B. Singer, N. Mehta, R. I. Bahar, R. Weiss, “Fetch Halting on Critical Load Misses,” in Workshop on Logic and Synthesis, Temecula Creek, CA, June 2004.

S. Bohidar, K. Nepal, R. I. Bahar, “Accurate Keeper Sizing using ADD-based Models of Subthreshold Leakage,” in Workshop on Logic and Synthesis, Temecula Creek, CA, June 2004.

N. Mehta, B. Singer, R. I. Bahar, M. Leuchtenburg, and R.Weiss, “Fetch Halting on Critical Load Misses,” IEEE/ACM International Conference on Computer Design, San Jose, CA, October 2004, pp. 244-249.

Y. Bai and R. I. Bahar, “Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm,” IEEE/ACM International Conference on Computer Design, San Jose, CA, October 2004, pp. 54-57.

T. Moreshet and R. I. Bahar, “Effects of Speculation on Performance and Issue Queue Design,” IEEE Transaction on VLSI, Vol. 12, No. 10, October 2004, pp. 1123–1125. Transaction brief.

2003

E. Chi, A. M. Salem, R. I. Bahar, and R. Weiss, “Combining Software and Hardware Monitoring for Improved Power and Performance Tuning,” Boston Area Architecture Workshop (BARC-2003), Cambridge, MA, January, 2003.

E. Chi, A. M. Salem, R. I. Bahar, and R. Weiss, “Combining Software and Hardware Monitoring for Improved Power and Performance Tuning,” Workshop on Interaction Between Compilers and Computer Architectures, Anaheim, CA, February, 2003.

Y. Bai and R. I. Bahar, “A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors,” Annual Symposium on Very Large Scale Integration, Tampa, FL, February, 2003, pp. 139-146.

J. Chen, J. Mundy, Y. Bai, S.-M. C. Chan, P. Petrica, and R. I. Bahar, “A Probabilistic Approach to Nano-computing,” in the 2nd Workshop on Non-Silicon Computation, San Diego, CA, June 2003.

J. Chen, J. Mundy, and R. I. Bahar, “A Probabilistic-based Design Methodology for Nanoscale Computer Architectures,” in the Workshop on Logic and Synthesis, Laguna Beach, CA, June 2003.

T. Moreshet and R. I. Bahar, “Power-Aware Issue Queue Design for Speculative Instructions,” Design Automation Conference, Anaheim, CA, June, 2003, pp. 634-637.

R. I. Bahar, J. Mundy, and J. Chen, “A Probabilistic-Based Design Methodology for Nanoscale Computation,” Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 2003, pp. 480-486.

H.Y. Song, S. Bohidar, R. I. Bahar, and J. Grodstein, “Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current,” International Conference on Computer Design, San Jose, CA, October 2003, pp. 70-75.

2002

T. Moreshet and R. I. Bahar, “Complexity-Effective Design Choices in Deeply Pipelined Processors,” Workshop on Complexity-Effective Design, held in conjunction with the International Symposium on Computer Architecture, Anchorage, AK, May 2002.

H. Y. Song, R. I. Bahar, and J. Grodstein, “Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations,” International Workshop on Logic and Synthesis, New Orleans, LA, June 2002.

2001

R. Maro, Y. Bai, R. I. Bahar, “Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processor,” Springer-Verlag Lecture Notes in Computer Science. Vol. 2008, 2001, pp. 97–111. Originally appeared in the International Workshop on Power-Aware Computing, November 2000.

R. I. Bahar and S. Manne, “Power and Energy Reduction via Pipeline Balancing,” ACM/IEEE International Symposium on Computer Architecture, Goteborg, Sweden, July 2001, pp. 218-229.

H. Y. Song, R. I. Bahar, and J. Grodstein “An ADD-Based Symbolic Analysis of Leakage Current in CMOS Circuits,” International Workshop on Logic and Synthesis, Lake Tahoe, CA, June 2001.

2000

R. I. Bahar, E. T. Lampe, E. Macii, “Power Optimization of Technology-Dependent Circuits Based on Symbolic Computation of Logic Implications,” ACM Transactions on Design Automation of Electronic Systems. July 2000, pp. 267–293.

R. Maro, Y. Bai, R. I. Bahar, “Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processor,” Workshop on Power-Aware Computer Systems, Cambridge, MA, November 2000.

1999

G. Albera, R. I. Bahar, “Power/Performance Advantages of Victim Buffer in High-Performance Processors,” IEEE Volta International Workshop on Low Power Design, Como, Italy, March 1999, pp. 43-51.

B. R. Fisk, R. I. Bahar, “The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency,” IEEE International Conference on Computer Design, Austin, TX, October 1999, pp. 538-543.

1998

R. I. Bahar, G. Albera, “Performance Analysis of Wrong-Path Data Cache Accesses”, Workshop on Performance Analysis and its Impact on Design, held in conjunction with the International Symposium on Computer Architecture, Barcelona, Spain, June, 1998.

G. Albera, R. I. Bahar, “Power and Performance Tradeoffs using Various Cache Configurations,” Power-Driven Microarchitecture Workshop, held in conjunction with the International Symposium on Computer Architecture, Barcelona, Spain, June, 1998.

R. I. Bahar, G. Albera, S. Manne, “Power and Performance Tradeoffs using Various Caching Strategies,” IEEE International Symposium on Low Power Electronics and Design, Monterey, CA, August 1998, pp. 64–69.

R. I. Bahar, B. Calder, D. Grunwald, “A Comparison of Software Code Reordering and Victim Buffers,” Workshop on Interaction Between Compilers and Computer Architectures, October, 1998. Also appeared in ACM SIGARCH Computer Architecture News, Vol. 27, No. 1, March 1999.

1997 and earlier

R. Badeau, et al., “A 100-MHz Macropipelined VAX Microprocessor,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, November 1992, pp. 1585-1598.

R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, F. Somenzi, “Algebraic Decision Diagrams and their Applications,” ACM/IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1993, pp. 188–191.

R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, F. Somenzi, “Timing Analysis of Combinational Circuits using ADDs,” IEEE European Conference on Design Automation, Paris, France, February 1994, pp. 625–629.

R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, F. Somenzi, “An Application of ADD-Based Timing Analysis to Combinational Low Power Re-Synthesis,” ACM/IEEE International Workshop on Low Power Design, Napa, CA, April 1994, pp. 39–44.

R. I. Bahar, G. D. Hachtel, E. Macii, F. Somenzi, “A Symbolic Method to Reduce Power Consumption of Circuits Containing False Paths,” ACM/IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1994, pp. 368–371.

A. Pardo, R. I. Bahar, S. Manne, P. Feldmann, G. D. Hachtel, F. Somenzi, “CMOS Dynamic Power Estimation Based On Collapsible Current Transistor Modeling,” IEEE International Symposium on Low Power Design, Dana Point, CA, April 1995, pp. 111–116.

S. Manne, A. Pardo, R. I. Bahar, G. D. Hachtel, F. Somenzi, E. Macii, M. Poncino, “On Computing the Maximum Power Cycles of a Sequential Circuit,” ACM/IEEE Design Automation Conference, San Francisco, CA, June 1995, pp. 23–28.

R. I. Bahar, F. Somenzi, “Boolean Techniques for Low Power Driven Re-Synthesis”, ACM/IEEE International Conference on Computer Aided Design, Santa Clara, CA, November 1995, pp. 428–432.

R. I. Bahar, M. Burns, G. D. Hachtel, E. Macii, H. Shin, F. Somenzi, “Symbolic Computation of Logic Implications for Technology-Dependent Low-Power Synthesis,” International Symposium on Low Power Electronics and Design, Monterey, CA, August 1996, pp. 163–168.

R. I. Bahar, E. A. Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, F. Somenzi, “Algebraic Decision Diagrams and their Applications,” Springer Journal of Formal Methods in Systems Design. Vol. 10, No. 2, April 1997, pp. 171-206.

R. I. Bahar “Symbolic Computation of Satisfiability and Observability Based Implications for Logic Optimization,” IEEE North Atlantic Test Workshop, West Greenwich, RI, May 1997, pp. 85–92.

R. I. Bahar, H. Cho, G. D. Hachtel, E. Macii, F. Somenzi, “Symbolic Timing Analysis and Re-Synthesis for Low Power of Combinational Circuits Containing False Paths,” IEEE Transactions on Computer-Aided Design of Integrated Circuits (TCAD) , Vol. 16, No. 10, October 1997, pp. 1101-1115.