View the entire paper (requires a Postscript-capable viewer)We present a boolean technique to reduce power consumption of combinational circuits which have already been optimized for area and delay and then mapped onto a library of gates. Starting with a mapped circuit enables us to obtain more accurate information about its power dissipation. We can then use this information to more effectively re-synthesize the circuit to lower its power dissipation. In order to achieve a better optimization, we first cluster gates by collapsing two or more levels of gates into a single node. When optimizing each cluster, our method extends the algorithms used in ESPRESSO, by adding heuristics that bias the minimization toward lowering the power dissipation in the circuit. The results of our method, on a number of benchmark circuits, show a significant improvement in power savings compared to existing boolean techniques.
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