Lecture Notes and Readings
|
Week
|
Date
|
Lecture Notes
|
| 1 | September 5, 2006 | Lecture 1: Introduction |
| September 7, 2006 | Lecture 2: Pipelining | |
| 2 | September 12, 2006 | Lecture 3: Interlocks |
| September 14, 2006 | Lecture 4: Simple Superscalar Processors | |
| 3 | September 19, 2006 | Lecture 5: Register Renaming |
| September 21, 2006 | Lecture 6: Metaflow Architecture | |
| 4 | September 26, 2006 | Lecture 7: More Micro Data Flow |
| September 28, 2006 | Lecture 8: Branch Prediction | |
| 5 | October 3, 2006 | Lecture 9: More Branch Prediction |
| October 5, 2006 | Lecture 10: Efficient Memory Design | |
| 6 | October 10, 2006 | NO CLASS |
| October 12, 2006 | NO CLASS | |
| 7 | October 17, 2006 | Lecture 11: Memory Prefetching |
| October 19, 2006 | Lecture 12: Software Scheduling | |
| 8 | October 24, 2006 |
Lecture 13: VLIW and EPIC Architectures Introdcuting the IA-64 Architecture, by Huck et al., IEEE Micro, Oct. 2000 When Caches Aren't Enough: Data Prefetching Techniques, by VanderWiel and Lilja, IEEE Computer, July 1997 |
| October 26, 2006 |
Lecture 14: Simultaneous Multithreading Simultaneous Multithreading: A Platform for Next-Generation Processors, by Eggers et al., IEEE Micro, Sept./OCt. 1997 |
|
| 9 | October 31, 2006 | |
| November 2, 2006 |
Midterm Exam |
|
| 10 | November 7, 2006 |
NO CLASS |
| November 9, 2006 |
A Highly Configurable Cache Architecture for Embedded Systems, by Zhang et al., ISCA 2003. Discussion leader: Greg Howard (slides) Scribe: Nuno Alves (notes) |
|
| 11 | November 13, 2006 (Monday makeup class) |
MONTECITO: A DUAL-CORE, DUAL-THREAD ITANIUM PROCESSOR, by McNairy and Bhatia., IEEE Micro, March/April 2005. Discussion leader: Elif Alpaslan (slides) Scribe: Cesare Ferri (notes) |
| November 14, 2006 |
Programming with Transactional Coherence and Consistency (TCC), Hammond et al., ASPLOS 2004. Discussion leader: Cesare Ferri(slides) Scribe: Chia-En Chang (notes) |
|
| November 16, 2006 |
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor, Weaver et al., ISCA 2004. Discussion leader: Brendan Hargreaves(slides) Scribe: Greg Howard (notes) |
|
| 12 | November 20, 2006 (Monday makeup class) |
Fire-and-Forget: Load/Store Scheduling with No Store Queue at All, S. Subramaniam, G. Loh, MICRO 2006. Discussion leader: Chia-En Chang (slides) Scribe: Yiwen Shi (notes) |
| November 21, 2006 |
Neural Methods for Dynamic Branch Prediction, Jimenez, Lin., ACM Transactions on Computer Systems, Vol. 20, No. 4, November 2002, pp. 369-397 Discussion leader: Nuno Alves(slides) Scribe: Brendan Hargreaves (notes) |
|
| 13 | November 28, 2006 |
A Defect Tolerant Self-organizing Nanoscale SIMD Architecture, J. P. Patwardhan, V. Johri, C. Dwyer, A. R. Lebeck, ASLPOS 2006. Discussion leader: Yiwen Shi (slides) Scribe: Elif Alpaslan (notes) |
| November 30, 2006 |
Transactional Memory: Architectural Support for Lock-free Data Structures, M. Herlihy and J. E. Moss, ISCA 1993. Discussion leaders: Greg, Brendan, Cesare (slides) |
|
| 14 | December 5, 2006 |
Piecewise Linear Branch Prediction, D. A. Jimenez, ISCA 2005 Discussion leaders: Elif, Nuno (slides) |
| December 7, 2006 |
Memory Dependence Prediction Using Store Sets, G. Z. Chrysos and J. S. Emer, ISCA 1998. Discussion leaders: Yiwen, Chia-en (slides) |