//Verilog Custom Instruction Template
module my_mult(

dataa, // operand A <always required>
datab, // operand B <optional>
result // result <always required>
		
);


input [31:0]dataa;
input [31:0]datab;
output[31:0]result;
wire[63:0] myZ;

mult testMult(
		);

assign result = myZ[31:0];

endmodule


module mult(
		
			);

endmodule



module half_adder(
		
			  )

endmodule

module full_adder(
			
			  );


endmodule

//Use for loops to make the connections to make your array multiplier using full and half adders.